A soha meg nem jelent C65 tovább él:
Originally shared by mos6502
This week, an ambitious rebuild and enhancement of Commodore's never-released C65[1]. A few prototypes of this machine[2] have survived - it has a 4510 CPU which incorporates a 65CE02 core[3], running at 3.5MHz and a VIC-III graphics chip offering high(er) resolution graphics. The first surprise with the rebuild is a core running at 48MHz. Both the original and this rebuild by Paul Gardner-Stephen offer a C64-compatible mode, and a native mode with support for large amounts of banked RAM.
Most recently, Paul has noted[4] an idea to provide for 32-bit pointers in zero page, making for a flat memory model. As all opcodes are assigned, he's looking at schemes which use NOP, SED and CLD as prefixes, modifying the next instruction. As the CE02 implements most single-byte opcodes in a single cycle, and can't interrupt after such a single-cycle operation, the prefix can't be separated from the instruction by an interrupt.
Another idea in the 65GS02 is to have an 8-byte-wide path to memory, allowing for pairs of bytes to be read or written in a single cycle, and for an instruction with its operands to be read in one cycle.
There's also a special handling of accesses to the VIC register, so the CPU acts in RMW operations more like an NMOS 6502, for improved compatibility.
It's worth noting that the 65CE02 not only runs some opcodes a cycle or two faster than the 6502, but also has a z register, a relocatable zero page, and a 16bit stack pointer, either flat memory or relocated single page. For more, see
http://www.zimmers.net/cbmpics/cbm/c65/c65manual.txt
The C65GS project incorporates an even-more-improved VIC-IV, with better video resolutions and better sprites. There's some juggling for performance, because on-FPGA RAM is fast but not especially plentiful, and off-chip RAM is slower but large. (Present target is a Digilent Nexys4 board - $320 or half price to students - with 16Mbyte of RAM and lots of useful peripherals on board.)
For more info, see the blog, the github repo and the mailing list for the project:
http://c65gs.blogspot.com.au/
http://github.com/gardners/c65gs
https://groups.google.com/forum/#!forum/c65gs-development
And also there are more videos:
https://www.youtube.com/results?search_query=c65gs
Hot news on the list this week: Commodore's 4510/65CE02 may have a bug in decimal mode - investigations are proceeding. We've seen many emulators fall at this hurdle. For more on the CE02, see Michael Steil's notes at
http://www.commodore.ca/manuals/funet/cbm/documents/chipdata/65ce02.txt
[1] http://www.floodgap.com/retrobits/ckb/secret/65.html
[2] http://en.wikipedia.org/wiki/Commodore_65
[3] http://en.wikipedia.org/wiki/CSG_65CE02
[4] http://c65gs.blogspot.com.au/2014/11/easily-accessing-all-of-memory.html
https://www.youtube.com/watch?v=9HHFi8cagyg
Originally shared by mos6502
This week, an ambitious rebuild and enhancement of Commodore's never-released C65[1]. A few prototypes of this machine[2] have survived - it has a 4510 CPU which incorporates a 65CE02 core[3], running at 3.5MHz and a VIC-III graphics chip offering high(er) resolution graphics. The first surprise with the rebuild is a core running at 48MHz. Both the original and this rebuild by Paul Gardner-Stephen offer a C64-compatible mode, and a native mode with support for large amounts of banked RAM.
Most recently, Paul has noted[4] an idea to provide for 32-bit pointers in zero page, making for a flat memory model. As all opcodes are assigned, he's looking at schemes which use NOP, SED and CLD as prefixes, modifying the next instruction. As the CE02 implements most single-byte opcodes in a single cycle, and can't interrupt after such a single-cycle operation, the prefix can't be separated from the instruction by an interrupt.
Another idea in the 65GS02 is to have an 8-byte-wide path to memory, allowing for pairs of bytes to be read or written in a single cycle, and for an instruction with its operands to be read in one cycle.
There's also a special handling of accesses to the VIC register, so the CPU acts in RMW operations more like an NMOS 6502, for improved compatibility.
It's worth noting that the 65CE02 not only runs some opcodes a cycle or two faster than the 6502, but also has a z register, a relocatable zero page, and a 16bit stack pointer, either flat memory or relocated single page. For more, see
http://www.zimmers.net/cbmpics/cbm/c65/c65manual.txt
The C65GS project incorporates an even-more-improved VIC-IV, with better video resolutions and better sprites. There's some juggling for performance, because on-FPGA RAM is fast but not especially plentiful, and off-chip RAM is slower but large. (Present target is a Digilent Nexys4 board - $320 or half price to students - with 16Mbyte of RAM and lots of useful peripherals on board.)
For more info, see the blog, the github repo and the mailing list for the project:
http://c65gs.blogspot.com.au/
http://github.com/gardners/c65gs
https://groups.google.com/forum/#!forum/c65gs-development
And also there are more videos:
https://www.youtube.com/results?search_query=c65gs
Hot news on the list this week: Commodore's 4510/65CE02 may have a bug in decimal mode - investigations are proceeding. We've seen many emulators fall at this hurdle. For more on the CE02, see Michael Steil's notes at
http://www.commodore.ca/manuals/funet/cbm/documents/chipdata/65ce02.txt
[1] http://www.floodgap.com/retrobits/ckb/secret/65.html
[2] http://en.wikipedia.org/wiki/Commodore_65
[3] http://en.wikipedia.org/wiki/CSG_65CE02
[4] http://c65gs.blogspot.com.au/2014/11/easily-accessing-all-of-memory.html
https://www.youtube.com/watch?v=9HHFi8cagyg
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